This invention relates to methods of manufacturing an electronic device which comprises a thin-film field-effect transistor (hereinafter termed "TFT"), the transistor having a field-relief region which is of lower doping concentration than its drain region and which is formed in an area of lateral separation between the channel region and the drain region. The invention also relates to electronic devices which comprise such a TFT. The device may be, for example, an active-matrix liquid-crystal display or other flat panel display, or any other type of large area electronic device with TFTs, for example, a thin-film data store or an image sensor.
There is currently much interest in developing thin-film circuits with TFTs on glass and on other inexpensive insulating substrates for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the; switching elements of a cell matrix, for example, in a flat panel display as described in U.S. Pat. No. 5,130,829, the contents of which are hereby incorporated herein by reference. A recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon) as, for example, integrated drive circuits for such a cell matrix. Unfortunately, instabilities occur in the transistor characteristics of such TFTs, especially those fabricated with polycrystalline silicon formed using low temperature processes. Several instability mechanisms occur, for example, bias-induced state creation in the polycrystalline silicon, and hot carrier induced state creation and carrier trapping. The degradation of the transistor characteristics (for example, off-state leakage current, threshold voltage and on-state current) can seriously limit the use of such TFTs in such circuits.
Published European Patent Application EP-A-0 520 560, which corresponds to U.S. patent application Ser. No. 08/471,803, discloses one way of reducing such instabilities of TFTs in an electronic device. The thin-film field effect transistor has a channel region in a first area of a semiconductor film between source and drain regions of the transistor; the transistor has a gate coupled to the channel region for controlling current flow along a current path between the source and drain regions; and a field-relief region of lower doping concentration than the drain region is formed in the current path at an area where the channel region is laterally separated from the drain region. The whole contents of Ser. No. 08/471,803 (EP-A-0 520 560) are hereby incorporated herein by reference.
In the method of manufacture disclosed in EP-A-0 520 560, the drain region is formed by depositing a highly-doped semiconductor layer on an intermediate semiconductor layer on the face of the semiconductor film which provides the channel region. The intermediate layer is doped with a lower conductivity-determining dopant concentration than the highly-doped layer. Part of the highly-doped layer is removed from the intermediate lower-doped layer (over an area corresponding to the width of the channel region and a length typically in excess of 1 .mu.m) so as to laterally separate the drain region from the transistor channel region and thus to form an area of the intermediate layer which is not overlapped by the drain region. This non-overlapped area of the intermediate layer is not modulated by the gate and provides the field-relief region. The resulting device structure is highly successful in reducing the TFT instabilities.
However, considerable care is needed in this known manufacturing method in determining the end-point of the two etching steps, namely when to stop the etch-removal of the highly-doped drain region layer from the intermediate, lower-doped layer and when to stop the etch-removal of the intermediate, lower-doped layer from the semiconductor film. These end-points are normally set by performing each etching treatment for a pre-calculated time.